Course difference logic for use with digital magnetic compass

ABSTRACT

Logic circuitry for use with a digital compass for providing an output indication of the difference between an actual and an intended course. Digital signals provided by a digital compass are processed in conjunction with a digital signal representation of intended course position to provide an output signal representing course difference and which can be employed by display or automatic pilot apparatus.

United States Patent Fowler Nov. 13, 1973 COURSE DIFFERENCE LOGIC FORUSE 3,337,723 8/1967 Etnyre 235/15027 WITH DIGITAL MAGNETIC COMPASS3,596,069 7/1971 Burt 235/1502? [75] Inventor: John T. Fowler, Winthrop,Mass. [73] Assignee: The Laitram Corporation, New PrimaryExaminer""loseph Ruggiero Orleans Attorney-Joseph Weingarten et al.

[22] Filed: Nov. 22, 1972 [21] Appl. No.: 308,823 [57] ABSTRACT CI235/5026, Logic circuitry for use with a digital compass for pro-340/347 DD viding an output indication of the difference between v G016G06f 15/50 an actual and an intended course. Digital signalspro- [58]Field of Search 235/1505, 150.26, vid d b a di ital compass areprocessed in conjunc- 235/ 2; 340/3 7 AD. 347 tion with a digital signalrepresentation of intended 244/77 B course position to provide an outputsignal representing course difference and which can be employed by [56]References Cited display or automatic pilot apparatus.

UNITED STATES PATENTS 3,289,475 12/1966 Kenyon 33/352 X 10 Claims, 7Drawing Figures INV V LIGHT V V BINARY SIGNALS PHOTO GRAY FROM SENSORBINARY DECODER CODE ARRAY CONVERTER COUNTER DISK e LOAD SLOW FAST STOP210 CLOCK V CLOCK BINARY BINARY SENSE COURSE UP DECODER 212 INPUTCOUNTER SOURCE 7 V A TRIGGERED CLOCK 222 TENABLE AND PULSE TRAIN LOAD 24DETECTOR B K 214 A EXCL COURSE DIFF PMENIEDNBY 13 I975 SHE 0F 3PAIENTEDIIIIY 13 I975 31772503 SHEET 2 BF 3 /94 fi /2OO K204 K206 VLIGHT 5|GNAL$ PHOTO- GRAY- BINARY FROM sENsoR V BINARY UP DECODER CODEARRAY CONVERTER COUNTER DISK 0 O O O LOAD Fig. 13. A SLOW FAST STOP 2CLOCK CLOCK zos BINARY T BINARY sENsE 212 coURsE UP DECODER K INPUTcoUNTER soURcE TRIGGERED I CLOCK 222 I ENABLE AND PULSE TRAIN LOAD 224DETECTOR B A EXCL, COURSE DIFE PAIENTEUHHY1 I915 3; 772.503

sum 36F 3 ENABLE M CLOCK PULSES A Lil SENSE TO Y C1 GATE 222 Ma H COURSEDIFFERENCE LOGIC FOR USE WITH DIGITAL MAGNETIC COMPASS FIELD OF THEINVENTION BACKGROUND OF THE INVENTION In copending application Ser. No.284,362 of John T. Fowler entitled Magnetic Compass Having RemoteDigital Readout, and assigned to the assignee of the present invention,digital compass logic circuitry is shown and described for providing anoutput indication of compass position in response to digital electricalsignals detected from a coded compass disk. An optically sensiblecompass disk is employed having a predetermined sequence of Gray codednumbers providing single bit transitions between each number around thecomplete compass circle. The associated logic circuitry converts thedetected Gray code into binary form for decoding of compassposition. Formany purposes, it is desirable to provide an output indication of thedifference between an actual and intended course; for example, for usein automatic piloting systems to correct the course being steered. It isan object of the present invention to provide improved logic circuitryoperative to provide such indications of course difference.

SUMMARY OF THE INVENTION Briefly, the invention comprises logiccircuitry operative to receive a first plurality of digital signalsrepresenting an actual course position and a second plurality of digitalsignals representing'an intended course, and to provide an outputindication of the difference between the two courses together with anindication of the sense of course error. The signals representing actualcourse are usually provided by a digital compass such as that shown inthe copending application, identifled above. The signal indication ofthe intended course can be provided by a manually operable courseselector which can include an optically sensible disk similar to thatemployed in the digital compass and which is manually rotatable topositions that provide corresponding output indications of intendedcourse positions.

The Gray coded digital signals provided by the compass are converted tobinary form for subsequent processing by the logic circuitry. The mostsignificant bit of the Gray code detected from the compass disk is,however, effectively inverted prior to binary conversion, this inversionoffering an efficient means of transforming the detected Gray coded datainto a format for subsequent processing. The inversion of the mostsignificant bit of the detected Gray code provides a code which is thecomplement of the equivalent binary version of the detected Gray code.This converted binary number is then employed to preset a unidirectionalbinary counter operative under the government of a system clock to countto a predetermined final count which is detected by an associateddecoder circuit. The decoder circuit, upon detection of the final count,provides an output signal to the system clock to cause discontinuance ofthe clock pulses. These pulses provided by the system clockserve as aserial output signal representative of actual course position. Theoutput pulses from the system clock are applied as one input to a gatingcircuit, and are also applied to a second clock which provides clockpulses to a second unidirectional counter which is preset by a signalindication of intended course. Pulses from the second clock are alsoapplied as an input to the gating circuit which provides an outputrepresentative of course difference between actual and intended courseposition.

DESCRIPTION OF THE DRAWINGS The invention will be more fully understoodfrom the following detailed description taken in conjunction with theaccompanying drawings in which:

FIG. 1 is a cut-away pictorial view of a digital compass useful in theinvention;

FIG. 2 is a cut-away plan view of a code disk employed in the compass ofFIG. 1;

FIG. 3 is a block diagram representation of logic circuitry embodyingthe invention;

FIG. 4 is a diagrammatic representation of an intended course encoder,useful in the invention;

FIG. 5 is a schematic diagram of a triggered clock useful in theinvention; and

FIGS. 6A and 6B show waveforms useful in illustrating operation of theinvention.

DETAILED DESCRIPTION OF THE INVENTION A digital compass operative toprovide digital signals representing compass position and processedaccording to the invention is shown in FIG. 1 and is itself the subjectof copending application Ser. No. 279,723, as signed to the assignee ofthe present invention. The compass includes a spherical housing 10typically formed of upper and lower hemispheres l2 and 14, respectively,and with the confronting edges of the hemispheres terminating inrespective flanges l6 and 18 which mate to form the overall housing. Thehemispheres 12 and 14 of housing 10 are secured together by fasteners 20provided through openings in flanges 16 and 18. An O-ring 22 or othersuitable sealing element can be provided around the periphery of themating surfaces of the respective hemispheres to provide a sealedenclosure to prevent leakage of damping liquid contained within thecompass housing. The lower hemisphere 14 of housing 10 can be disposedwithin a cylindrical support 14 and secured thereto such as by fasteners26 to provide a convenient base structure for mounting the compass foruse in a marine vessel or other body in which it is to be employed.

A post 28 is provided at the top portion of hemisphere 12 and extendsradially inward by an amount less than the full radius of the sphericalenclosure. The post 28 can be integrally formed with hemisphere 12, asillustrated, or can be a separate element attached by any suitablemounting means. A gimbal assembly 30 is supported on the lower end ofpost 28 by a fastening screw 33, the gimbal assembly including agenerally U- shaped member 32 fastened as shown to post 28 by screw 33and supporting a first gimbal 34 by means of mounting pins 36 whichdefine a first axis about which gimbal 34 is rotatable. A second gimbal38 is disposed within gimbal 34 and supported-by pins 40 which define asecond axis orthogonal to the axis defined by pins 36 and about whichgimbal 38 is rotatable.

The inner gimbal 38 includes a generally cylindrical collar portionwhich extends at right angles to the axis defined by pins 40 and whichis employed to support the compass disk enclosure and associated codedisk for rotation therein. The collar portion includes a generallycylindrical shaft 42 which terminates at its lower extremity in anenlarged end portion 44 which is affixed to the upper plate 48 of anannular enclosure 50. The enlarged portion 44 can be molded or otherwisesecured to enclosure 50 to be integrally affixed for rotation therewith.The enclosure 50 is typically formed by a cup section 52 with thecircular top plate 48 secured to the periphery of cup 52 such as bymachine screws 54. The enclosure 50 is thereby suspended from the gimbalassembly 30 for maintenance of a generally horizontal disposition in thepresence of motion experienced by housing 10.

The code disk 56 is formed of a light transmissive material such asglass or plastic and is affixed to a centrally disposed hub 58 which hasoppositely extending shafts 60 and 62. The upper shaft 60 supports acylindrical pin 64 which cooperates with a bearing mounted within thecollar portion. The lower shaft 62 contains a pin 76 which cooperateswith a bearing provided in cylindrical member 78 which is secured withinan opening in cylindrical post 80 and secured therein by a set screw 82.The post 80 is affixed to enclosure 50 by means of a centrally disposedflange portion 84. The compass disk 56 is thus supported for rotation byits respective bearings which are adjusted to permit free rotation ofthe disk about the bearing axis.

A cylindrical magnet 86 is provided around hub 58 and is concentricallydisposed with respect to disk 56 and secured in engagement with thebottom surface thereof by any suitable means. The magnet has a magneticaxis aligned with the north-south axis of the disk. The cylindricalmagnet is preferable in maintaining the mass of the rotatable compassstructure near the center of rotation to minimize the torque necessaryto cause disk rotation and thereby enhance compass sensitivity. In analternative embodiment, one or more bar magnets can be provided inassociation with code disk 56. The code disk 56 is free to rotate aboutits axis to a position determined by the interaction of magnet 86 withthe earth s magnetic field to define a compass position which, as willbe described, is electro-optically sensed to provide a plurality ofdigital electrical signals for processing and display.

The compass structure is fabricated of suitable nonmagnetic materials.In a typical implementation the housing 10 is formed of a plasticmaterial such as LEXAN, while the gimbal assembly 30 is fabricated ofbrass, as is the hub 58 and associated disk supporting structure.

The coded disk 56 is illustrated more fully in FIG. 2 and is fabricatedof a light transmissive material, such as glass or plastic, and hasprovided on a surface thereof a plurality of concentric tracks eachhaving a different predetermined number of alternately lighttransmissive and opaque segments. Each track is coded to represent onebit of a multiple bit code, the number of tracks being selected toaccommodate the intended compass resolution. In the illustratedembodiment, nine concentric tracks, 57a-57i, are provided to producenine bit codes representing each degree of the 360 of the code disk. Theinnermost track 57a contains one opaque segment which occupies 180thereof, the other 180 segment being light transmissive, this trackserving as the most significant bit of the multiple bit code. Thesuccessive tracks 57b-57i extending outwardly of the disk containdifferent numbers of alternately light transmissive and opaque segmentswhich represent successive bit positions of the multiple bit code sensedat each angular position of the disk with respect to the sensor array94. The code disk per se is well known in the optical angle encoder artand need not be described at length in the present application.

A Gray or other cyclic binary code is employed having a sequence of codevalues such that transitions between each Gray code equivalent ofadjacent compass positions is accomplished with only a single bit changein the detected code including the transition between 0 and 359. Theprovision of a code having single bit transitions between each degreeposition throughout the compass circle is especially advantageous inimplementing the logical circuitry and in minimizing the ambiguoussensing of adjacent codes which can arise if the code disk is positionedwith the photosensor array aligned between adjacent degree positions. Byuse of Gray coding, the possible error or ambiguity is limited to only asingle bit or 1 in the embodiment described. In the illustratedembodiment, Gray code values are employed corresponding to desirednumerals from 76 to 435. The Gray code equivalent of decimal 76represents a 0 compass reading, while a Gray code equivalent of decimal435 represents a 359 reading.

A light emitting diode 92 or other suitable illumination source isprovided in the bottom wall of cup 52 in a position to direct lightthrough the coded tracks of disk 56 and connected to a circuit board 96by wires 97. Light transmitted through disk 56 is received by aphotosensor array 94 affixed to plate 48 of enclosure 50 and whichincludes a linear array of photocells each in light receivingrelationship with a respective track of disk 56 and each operative toprovide a respective output signal of a first value in response to lightreceived from a transmissive portion of the associated code track and ofa second value in response to the absence of light received from anoccluded portion of that code track. The array 94 thereby produces aplurality of digital signals which represent the coded equivalent of thecompass position as determined by the angular disposition of disk 56with respect to the compass housing 10.

The photosensor array 94 is connected to a printed circuit board 96 bymeans of leads 98, this circuit board also including associatedelectronic circuitry typically in the form of one or more integratedcircuit modules 100 which are interconnected to array 94 and to terminalposts 104 by etched conductive paths 102. In a preferred embodiment onlythree terminal posts need be employed for power, ground and dataconnections, respectively. Other terminal arrangements can, of course,be provided as is well known in the electronics art. Employment of asmall number of terminals is, however, advantageous in minimizing thenumber of interconnecting wires or paths which must be coupled from thecompass circuitry to the output cable. The circuit board 96 is mountedon plate 48 of enclosure 50 and is immersed in the damping liquid ofhousing 10 which provides a stabilized thermal environment for the electronic components. I

The cup portion 52 of enclosure 50 typically includes a rounded sidewallwhich conforms to the curvature of hemisphere 14 and which is spacedtherefrom by a predetermined amount. In operation, the housing 10 andenclosure 50 are both filled with a damping liquid, such as water, toprovide a separate damping environment for disk 56 and enclosure 50 andfor gimbal assembly 30. The housing is filled typically by means of afilling port 106 formed in post 28. Liquid enters enclosure 50 by meansof one or more passages or openings 108 provided, for example, throughthe bottom and top walls of cup portion 52. A plug 110 is threaded ontoscrew 33 as a closure for port 106 and is sealed for example by anO-ring 112 provided around a circumferential channel in plug 110, asshown.

The enclosure 50 is completely filled with damping liquid while thehousing 10 is substantially filled, leaving a small amount of air space115 to provide room for liquid expansion under varying termperatureconditions. The disk 56 is preferably of substantially smaller diameterthan that of enclosure 50 by an amount such that swirling of liquid nearthe periphery of enclosure 50 will not materially affect disk 56. In theillustrated embodiment, the disk 56 has a diameter of two inches whilethe internal diameter of enclosure 50 at its largest dimension is 4inches. The specific dimensions are, of course, a matter of choicedependent upon the particular operating characteristics andspecifications desired.

Electrical connection is made to the compass electronics by means of acable 114 secured for example by means of a sealing sleeve 1 16 whichterminates in a ring 118 disposed within a channel 119 provided in theupper portion of housing 10. A cover 120 encloses a junction box 122which includes terminal posts 124 each having an upper portion withinthe junction box for connection to respective wires 126 of cable 114,and a lower portion within hemisphere 12 to which connecting wires 128are couples from respective terminal posts 104. The interconnectingwires 128 can be braided together and are arranged in a path such asaround post 28 as shown, to provide slack sufficient to not impede thefree rotation of enclosure 50.

Considering the operation of the invention in a typical environmentaboard a ship, the compass housing 10 is installed such as by base 24 atany suitable position in the vessel and with the sensor array 94 alignedalong or parallel to the longitudinal axis of the vessel. The display ofcompass heading is usually provided at a position remote from thecompass structure itself since the electrical output signals can betransmitted readily to remote locations. Since the compass rotor is notvisually viewed, the compass structure can be mounted at variouslocations which would be unsuitable for conventional visually readablecompasses. The compass can, for example, be located in the hold of aship or even at locations at which rolling, pitching and yawing motionsare exaggerated since the compass disk is well damped by its enclosingfluid, while the disk enclosure and supporting gimbal assembly are alsodumped by the separate liquid medium of housing 10.

The logic circuitry of the invention is illustrated in FIG. 3 and isoperative in response to digital signals received from the compass andfrom digital signals received from an intended course input source toprovide an output indication of the difference between actual andintended course. The photosensor array 94 provides a plurality ofdigital signals representing the Gray code sensed from disk 56, andthese signals are applied to a Gray-to-binary converter 200. The digitalsignal representing the most significant bit of the detected Gray codeis applied to converter 200 by way of an inverter 202 to provideinversion of this most significant bit. The output signals of converter200 are applied to a binary up-counter 204, the output'of which isapplied to a decoder 206.

The inversion of the most significant bit by inverter 202 of the codeapplied to converter 200 causes a binary output from the converter whichis the complement of the equivalent binary number represented by theGray-coded signal read from the code disk. The inversion of the mostsignificant bit of the code applied to converter 200 effectively invertsthe entire applied code by operation of the Gray-to-binary converter.The converter itself is well known in the electronics art, a typicalimplementation being described in Electronic Analog-to-DigitalConversion, H. Schmid, Van Nostrand, Reinhold Co. (1970) pages 312-313.The reciprocal relationship between the input Gray code and theconverted binary output of converter 200 offers particular advantages interms of efficient and relatively simple logical processing. Suchreciprocal code relationship allows use of a unidirectional counterwhichis a less complex circuit than a reversible or bidirectional counter,which would otherwise be required. Also, the reciprocal coderelationship permits the generation of a direct output representative ofcourse position without additional conversions of the code. Theinversion of the most significant bit of the input Gray code canalternatively be provided by inversion of the code segments on the mostsignificant bit track of the code disk, rather than by electronicinverter 202 in the associated logic circuitry.

A fast clock 208 is enabled by a slow clock 210 and provides clocksignals to counter 204 for governing the counting operation. The slowclock 210 determines the sampling rate at which the course positions areprocessed, and provides a load command to enable the.

entry of data into counter 204. The output signal from decoder 206 isapplied as a stop signal to fast clock 208 to discontinue the clockingoperation thereof. This output signal, which is in the form of a trainof one or more pulses, is representative of the actual course positionas detected by the digital compass and is applied to a triggered clock212 and to a pulse train detector 214. The pulse train provided by clock208 can also be applied to an output display or other utilizationapparatus for indication of actual compass heading.

A course input source 216 provides a plurality of digital signals whichrepresent an intended course and which are applied to a binaryup-counter 218. The output signals from counter 218 are applied to adecoder 220. The clock 212 applies clock signals via an AND gate 222 tocounter 218, and as one input to an exclusive OR gate 224. The gate 224also receives as an input the pulse train provided by clock 208. Theoutput signal from decoder 220 is applied as an input signal to gate222, and also serves as an output indication of the sense of coursedifference. The magnitude of course difference is indicated by the pulsesignals from OR gate 224.

The binary course input source is typically a manually adjustable devicefor selecting an intended course and for providing a binary signalrepresentation of the selected course. An embodiment of such an input'source is illustrated in FIG. 4 and includes a light transdisk issupported for rotation relative to a photosensor array 234 which isdisposed along a radius of the disk and which includes a plurality ofphotosensors each operative to sense light received from a respectivetrack 232. A light source such as lamp 236 is provided adjacent theopposite surface of disk 230 as array 234 for illuminating the severaltracks of the disk. In the illustrated embodiment, the disk is manuallyrotatable by means of a knob 238 having affixed thereto a pointer 240which indicates the selected course heading depicted on associatedvisually readable scale 242. For each angular position of disk 230, amultiple bit signal is provided by array 234 representative of theselected course. The disk 230 provides the same resolution as thecompass disk, which is 1 in the embodiment under discussion.

During operation, the code disk will be at an angular position inaccordance with the earths magnetic field such that the photosensorarray 94 is aligned with respect to the disk to provide a plurality ofoutput signals representing the compass heading in Gray-coded form.These signals are applied to the Gray-to-binary converter 200 with themost significant bit thereof inverted by inverter 202 prior to. itsapplication to the converter. The binary coded output of converter 200is applied to up-counter 204, which under the control of clock pulsesprovided by fast clock 208, causes the counter to be loaded with thenumber provided by converter 200 and to increment the counter to apredetermined final count which is then sensed and decoded by decoder206.

In the implementation described, the counter 204 operates to a finalcount which is the binary equivalent of decimal 435 which is detected bydecoder 206 and which provides, upon such detection, a stop signal tofast clock 208 to discontinue its operation. The decoder 206 istypically a NAND gate for receiving the input signals representing thenumber to be decoded. The number of pulses provided by fast clock 208 tocounter 204 is equal to the difference between the initial and finalcounts of counter 204 and is of a number equal to the measured course indegrees. The number of pulses representing the compass course is amatter of choice depending upon system requirements. For example,decoder 206 can be operative to detect the binary equivalent of decimal436 which will permit fast clock 208 to produce output pulses of anumber one higher than the measured course. The extra pulse is usefultypically to reset an associated display of compass position. Thecounter 218 and decoder 220 are the same as counter 204 and decoder 206and operate similarly. The counter 218 is loaded with a binary countfrom input source 216 and operates to a predetermined final count, thebinary equivalent of decimal 435, detected by decoder 220. This decoderprovides, upon detection of the final count, an output signal which isoperative to stop the incrementing of counter 218, and as a senseindication of course difference.

The triggered clock 212 operates at its own rate in the absence of anoverriding signal received from clock 208. In the presence of such areceived signal, the clock output is forced to operate at the rate ofthe received signal. The counter 218 can only operate during the timeinterval permitted by the load signal from detector 214, and during thisinterval, the counter can increment from the initial count entered fromsource 216 to either the count sensed by decoder 220 or the highestcount which is within the enabling interval, whichever first occurs. Theenabling interval is sufficient to allow processing of the greatestpossible course difference.

The triggered clock is typically implemented by the circuit of FIG. 5which includes a NAND GATE 250 receiving the enable signal from pulsetrain detector 214 and clock pulses (A) via a coupling capacitor C1. Theoutput of gate 250 is coupled to an inverting amplifier 252, the outputof which provides the clock signals for gate 222. A feedback path isprovided across inverter 252 by a capacitor C2 and a resistor R1, whilea feedback path across gate 250 is provided by resistor R1 and aresistor 2R1. In the absence of clock pulses (A) from fast clock 208,the circuit operates at a frequency essentially determined by thecombination of resistor R1 and capacitor C2 and which is somewhat slowerthan the frequency of these pulses. In the presence of clock pulses (A)which serve to override the normal clocking operation of the circuit,pulses are provided by gate 252 at a faster rate corresponding to therate of the received pulses.

Upon receipt of clock pulses from fast clock 208, the pulse traindetector 214 generates a load signal to permit the entry into counter218 of a binary code from source 216 representing an intended course.The pulse train detector also enables triggered clock 212 for provisionof clock pulses to counter 218 via AND gate 222. The AND gate is enabledby the output signal of decoder 220 which is present at one binary leveluntil the time the decoder detects the predetermined final count ofcounter 218. The exclusive OR circuit 224 receives, as one input, thepulse train from clock 208, and as a second input, the pulses providedby AND gate 222. It will be appreciated that the exclusive OR circuit224 provides an output pulse only when one or the other of its inputsignals is present and thus is efi'ective to provide an outputindication of the difference between its received input signals andrepresenting the difference between an actual and intended course.

The triggered clock 212 provides an output pulse for each pulse receivedfrom clock 208, and counter 218 is incremented a number of timesrepresented by the number of pulses received from clock 208. In theabsence of pulses (A) applied to clock 212 by clock 208, the triggeredclock provides output pulses so long as the enable signal is presentfrom detector 214. Clock pulses are thus provided by clock 212 for theduration of the time interval defined by the load signal from detector214.

As an example, assume that an actual course sensed by the digitalcompass is 3, and the intended course to be steered by a vessel is 2.With reference to FIG. 6A, the pulse train A provided by fast clock 208representing the actual course will contain three pulses. The pulsetrain B from AND gate 222 will contain two pulses representingthe-intended course. The exclusive OR gate 224 will provide an outputpulse only when a pulse is applied to either but not both of the inputsthereof, and since pulses are present in the first and second pulsepositions of respective pulse trains A and B, gate 224 will provide nooutput during reception of these pulses. However, the third pulse ofpulse train A is present at a time when no pulse is provided by pulsetrain B, and gate 224 thus provides one output pulse indicative of a 1course difference. The output signal from decoder 220 changes from afirst to a second logic level upon receipt of the detectable final countfrom counter 218. This second logic level present during the outputpulse from gate 224 indicates the sense of the course difference, beingin this case the actual less the intended course.

Assume now that the actual course is 2 while the intended course is 3.Operation of the invention is similar to that described immediatelyabove except that the sense signal from decoder 220 will denote that theintended course is greater than the actual course. As seen in FIG. 6B,the sense signal will change from a first to a second logic level afterproduction of the third pulse of pulse train B which is after theproduction of the output pulse from gate 224. The sense signal thereforeis of a first logic level during the presence of the course differencesignal to denote that the course difference represents the intended lessthe actual course.

It will be appreciated that the invention is not limited to theparticular implementations-shown and de-- scribed. For example, thelogic circuitry of the invention is not limited to use with magneticcompasses alone, but is more generally useful for the processing ofdigital signals provided by other types of angle encoders or otherdevices wherein the difference between digital codes is desired.Accordingly, it is not intended to limit the invention by what has beenparticularly shown and described except as indicated in the appendedclaims.

What is claimed is:

1. For use with a compass providing Gray coded signals representative ofcompass headings, logic circuitry operative in response to said signalsto provide an output indication of course difference comprising:

converter means for converting said signals to binary coded signalsrepresenting a binary code which is the complement of the binaryequivalent of a received Gray code from said compass;

first unidirectional binary counter means;

means for presetting said first counter means with a binary numberrepresentative of an actual course sensed by said compass;

first clock means for providing first clock pulses to increment saidfirst counter means from said preset binary number to a predeterminedcount;

first decoder means coupled to the output of said first counter meansand operative in response to said predetermined count to provide anoutput signal operative to stop operation of said first clock means;

said first clock pulses being of a number representative of actualcompass heading; second unidirectional binary counter means;

means for presett'ing said second counter means with a binary numberrepresentative of an intended course; second clock means for providingsecond clock pulses to increment said second counter means for thenumber entered therein to a predetermined count;

second decoder means operative in response to the predetermined countfrom said second counter means to provide an output signal operative tostop provision of said second clock pulses; and

logic circuit means operative in response to said first and said secondclock pulses to provide course difference outputpulses of a numberrepresentative of the difference between said actual and intendedcourses;

said output signal from said second decoder means being of a valueduring production of said course difference pulses representative of thesense of course difference.

2. For use with a compass providing Gray coded signals representative ofcompass headings, logic circuitry operative in response to said signalsto provide an output indication of course difference comprising:

converter means for converting said signals to binary coded signalsrepresenting a binary code which is the complement of the binaryequivalent of a received Gray code from said compass; a firstunidirectional binary counter receiving the binary output signals fromsaid converter means;

first decoder means coupled to the output of said counter and operativeto provide an output signal in response to a predetermined counttherefrom;

first clock means for providing clock pulses to increment said counterfrom the binary number entered therein to a predetermined higher countat which said first decoder means is responsive;

said decoder output signal being operative to stop operation of saidfirst clock means;

the clock pulses provided by said first clock means being of a numberrepresentative of an actual compass course;

means for providing a binary signal representation of an intendedcourse; a second unidirectional binary counter receiving the binarysignals from said'intended course means;

second decoder means coupled to the output of said second counter andoperative to provide an output signal in response to a predeterminedcount therefrom;

pulse detector means operative in response to the clock pulses from saidfirst clock means to provide a load signal to said second counter and anenable signal; second clock means enabled by said enable signal andoperative in response to the clock pulses from said first clock means toprovide corresponding clock pulses for said second counter and alsooperative in the absence of receivedrclock pulses from said first clockmeans to provide clock pulses for said second counter so long as saidenable signal is present; first gate means receiving the clock pulsesfrom said second clock means and the output signal from said seconddecoder means and operative to apply clock pulses to said second countermeans;

second gate means receiving the clock pulses from said first clock meansand from said first gate means and operative to provide output pulses ofa number representative of the difference between said actual andintended courses;

the output signal from said second decoder means having a binary valueduring the production of said course difference pulses representative ofthe sense of course difference.

3. The invention according to claim 2 wherein said Gray coded signalsrepresent a selected code sequence of Gray coded values which provideunambiguous transition throughout the compass circle.

4. Theinvention according to claim 2 wherein said Gray coded signalsrepresent a sequence of Gray coded values corresponding to decimalnumbers from 76 to 435, The invention the Gray coded equivalent ofdecimal 76 representing a compass heading of the Gray coded equivalentof decimal 435 representing a compass heading of 359.

5. The invention according to claim 2 wherein said converter meansincludes:

a Gray-to-binary converter; and

means for inverting the signal representing the most significant bit ofsaid Gray code prior to application of said bit to said Gray-to-binaryconverter.

6. The invention according to claim 2 wherein said first clock meansincludes;

a first clock operative at a predetermined rate for providing said clockpulses; and

a slow clock operative at a predetermined lower rate than the rate ofsaid first clock and operative to control the sampling rate at whichsignals are processed.

7. The invention according to claim 5 wherein said second clock meansincludes:

a triggered clock circuit operative in the presence of said enablesignal to provide clock pulses at a predetermined rate, and operative inthe presence of said enable signal and clock pulses received from saidfirst clock means to provide clock pulses at a faster rate equal to therate of said received clock pulses.

8. The invention according to claim 7 wherein said pulse detector meansincludes:

a pulse train detector operative to provide said load and enable signalsfor the duration of the clock signals received from said first clockmeans and for a predetermined further interval sufficient to permitprocessing of the greatest possible course difference.

9. The invention according to claim 8 wherein said second gate meansincludes:

an exclusive OR gate operative to provide an output pulse only in thepresence of either a clock pulse from said first clock means or saidfirst gate means, thereby to provide said output pulses of a numberrepresentative of course difference.

10. The invention according to claim 9 wherein said first gate meansincludes:

a AND gate operative in the presence of an output signal from saidsecond decoder means of first binary level to apply clock pulses to saidsecond counter means and said second gate means.

UNITED STATES PATENT OFFICE a CERTIFICATE OF 'CORRECTIONQ Patent,772,503 wmed November 13;" 19-73 Q-[i Inventor(s) John T wler It is crtified that error appears in. the above-identified" pateni flf g andthat said Letters Patent are hereby corrected as shown below:

Column 2, line46, "support 14" should read I -support "24-- e I Column-5, line 61, "course" should read --courses- 7 Column 10, line 64,"transition" should read --transiti.Qns-. I

Claim 4, line 65, 'Theinvehtion should read .--Th inve'ntion-.

' Cla im4, line 68, delete "The invention".

' '-first clock" should read Claim-'6, lines 12 and 15, -fast CLOCK-"m.

Signed and sealed this 21st dayA-of May 197A.

(SEAL) Attest:

' c. IMF-{SHALL mum EDWARD PLFLETCHE a,

Commlssloner of Patents Attesting Officer USCOMM-DC 60376-P69 i 0.5.Govuumzm nnmua ornc: I94" o-au-au FORM PO-IOSO (10-69) UNITED STATESPATENT OFFICE m J. CER'IIFI'CATE (DP-CORRECTION; Patent No. 3,772,503Dated November 15 1973 Inventor(s) John T Wler It is certified thaterror appears in the above-identified"patent/ i?- and that said LettersPatent are hereby corrected as shown below:

Column 2, line 46, "support 14" should read --support 24--.

Column -5, line 61, "course" should read --courses I vColumn 10, line64, "transition" should read --transit'i,ons--.

Claim 4, line 65, "Theinvention" should read ,--The invention". I

' Claim 4, line 68, delete "The invention".

Claifn 6, lines 12 and 15, "first clock" should read -fast cl ock--..

Signed and sealed this 21st da; 701 y 9 (SEAL) Attest:

roman HELETCHER, 1 d i c. MARSI-EALL DANE-I Attesting OfficerCommissioner of Patents FORM Po-wso (10-69) uscoMM-oc 60376-P69 i .5.GOVERNMENT PIINI'ING OFFICE: U II 0-306-334

1. For use with a compass providing Gray coded signals representative ofcompass headings, logic circuitry operative in response to said signalsto provide an output indication of course difference comprising:converter means for converting said signals to binary coded signalsrepresenting a binary code which is the complement of the binaryequivalent of a received Gray code from said compass; firstunidirectional binary counter means; means for presetting said firstcounter means with a binary number representative of an actual coursesensed by said compass; first clock means for providing first clockpulses to increment said first counter means from said preset binarynumber to a predetermined count; first decoder means coupled to theoutput of said first counter means and operative in response to saidpredetermined count to provide an output signal operative to stopoperation of said first clock means; said first clock pulses being of anumber representative of actual compass heading; second unidirectionalbinary counter means; means for presetting said second counter meanswith a binary number representative of an intended course; second clockmeans for providing second clock pulses to increment said second countermeans for the number entered therein to a predetermined count; seconddecoder means operative in response to the predetermined count from saidsecond couNter means to provide an output signal operative to stopprovision of said second clock pulses; and logic circuit means operativein response to said first and said second clock pulses to provide coursedifference output pulses of a number representative of the differencebetween said actual and intended courses; said output signal from saidsecond decoder means being of a value during production of said coursedifference pulses representative of the sense of course difference. 2.For use with a compass providing Gray coded signals representative ofcompass headings, logic circuitry operative in response to said signalsto provide an output indication of course difference comprising:converter means for converting said signals to binary coded signalsrepresenting a binary code which is the complement of the binaryequivalent of a received Gray code from said compass; a firstunidirectional binary counter receiving the binary output signals fromsaid converter means; first decoder means coupled to the output of saidcounter and operative to provide an output signal in response to apredetermined count therefrom; first clock means for providing clockpulses to increment said counter from the binary number entered thereinto a predetermined higher count at which said first decoder means isresponsive; said decoder output signal being operative to stop operationof said first clock means; the clock pulses provided by said first clockmeans being of a number representative of an actual compass course;means for providing a binary signal representation of an intendedcourse; a second unidirectional binary counter receiving the binarysignals from said intended course means; second decoder means coupled tothe output of said second counter and operative to provide an outputsignal in response to a predetermined count therefrom; pulse detectormeans operative in response to the clock pulses from said first clockmeans to provide a load signal to said second counter and an enablesignal; second clock means enabled by said enable signal and operativein response to the clock pulses from said first clock means to providecorresponding clock pulses for said second counter and also operative inthe absence of received clock pulses from said first clock means toprovide clock pulses for said second counter so long as said enablesignal is present; first gate means receiving the clock pulses from saidsecond clock means and the output signal from said second decoder meansand operative to apply clock pulses to said second counter means; secondgate means receiving the clock pulses from said first clock means andfrom said first gate means and operative to provide output pulses of anumber representative of the difference between said actual and intendedcourses; the output signal from said second decoder means having abinary value during the production of said course difference pulsesrepresentative of the sense of course difference.
 3. The inventionaccording to claim 2 wherein said Gray coded signals represent aselected code sequence of Gray coded values which provide unambiguoustransition throughout the compass circle.
 4. Theinvention according toclaim 2 wherein said Gray coded signals represent a sequence of Graycoded values corresponding to decimal numbers from 76 to 435, Theinvention the Gray coded equivalent of decimal 76 representing a compassheading of 0*, the Gray coded equivalent of decimal 435 representing acompass heading of 359*.
 5. The invention according to claim 2 whereinsaid converter means includes: a Gray-to-binary converter; and means forinverting the signal representing the most significant bit of said Graycode prior to application of said bit to said Gray-to-binary converter.6. The invention according to claim 2 wherein said first clock meansincludes; a first clock operative at a predeteRmined rate for providingsaid clock pulses; and a slow clock operative at a predetermined lowerrate than the rate of said first clock and operative to control thesampling rate at which signals are processed.
 7. The invention accordingto claim 5 wherein said second clock means includes: a triggered clockcircuit operative in the presence of said enable signal to provide clockpulses at a predetermined rate, and operative in the presence of saidenable signal and clock pulses received from said first clock means toprovide clock pulses at a faster rate equal to the rate of said receivedclock pulses.
 8. The invention according to claim 7 wherein said pulsedetector means includes: a pulse train detector operative to providesaid load and enable signals for the duration of the clock signalsreceived from said first clock means and for a predetermined furtherinterval sufficient to permit processing of the greatest possible coursedifference.
 9. The invention according to claim 8 wherein said secondgate means includes: an exclusive OR gate operative to provide an outputpulse only in the presence of either a clock pulse from said first clockmeans or said first gate means, thereby to provide said output pulses ofa number representative of course difference.
 10. The inventionaccording to claim 9 wherein said first gate means includes: a AND gateoperative in the presence of an output signal from said second decodermeans of first binary level to apply clock pulses to said second countermeans and said second gate means.